Precision clock synthesis is important in a number of fields. For this purpose, an output clock may be synthesized from a reference clock input tied to some standard reference using a digital phase locked loop (DPLL). In normal operation, the DPLL will synchronize its output clock to the reference clock.
In order to allow for failure or drift of the reference clock, a plurality (two or more) reference clocks are provided. The DPLL is locked to a selected one of them. In the event that the selected reference clock fails or drifts too far, the input of the DPLL is switched to an alternative reference clock.
It is important that switching between the reference clocks occurs smoothly without a phase glitch caused by momentary loss of synchronization. Prior art clock synthesizers are designed to provide what is known as hitless reference switching to ensure a smooth transition between reference clocks.
Where the clock synthesizer is used to provide a stable clock source in certain applications, such as in the dual PLL crystal synchronization circuit described in U.S. Pat. No. 9,444,470, the contents of which are herein incorporated by reference, frequency stabilization can be more important than the mere lack of phase movement that is ensured by hitless switching. In hitless switching, there is no phase or frequency jump at the time of the switching to a new reference clock with slightly different frequency and phase, but the frequency and phase of the output clock will gradually drift to the new frequency and phase determined by the new reference input clock as a result of the inherent properties of the PLL. This frequency drift is unacceptable in applications such as that described in U.S. Pat. No. 9,444,470, where a highly stable clock source whose frequency does not change over time is required. The synthesizer output frequency should remain stable at a constant frequency during and after reference switching even if there is a frequency offset between the two reference clocks, or at the very least should drift to the frequency of the new reference clock at a delayed and potentially settable rate after reference switching. The problem addressed by the invention is how to provide a clock synthesizer that allows for switching between reference clocks while meeting these criteria.